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ISL59834
Data Sheet June 11, 2008 FN6268.1
Quad Channel, Single Supply, Video Reconstruction Filter with On-Board Charge Pump
The ISL59834 is a quad channel, single supply, video reconstruction filter with integrated charge pump. It is designed to operate on a single supply (3.0V to 3.6V) and generate its own negative supply (-1.5V) using a regulated charge pump. Input signals to the ISL59834 can be AC- or DC-coupled. When AC-coupled, the backporch clamp sets the blank level to ground at the output. Channels 1 and 3 have a sync detector whose output is available at SYNC_OUTA and SYNC_OUTB, respectively. SYNC_INA and SYNC_INB are inputs that provide timing for Channel 2 and Channel 4, respectively. Channel 2 and Channel 4 have keyed clamps, which set the outputs to ground when SYNC_INA or SYNC_INB are driven to the logic high state. Each of the four outputs are capable of driving two DC or AC-coupled standard video loads. The ISL59834 features a 4th order Butterworth reconstruction filter that provides a 9MHz nominal -3dB frequency and 40dB of attenuation at 27MHz. Nominal operational current is 63mA. When powered down, the device draws 5A maximum supply current. The ISL59834 is available in a 44 Ld 7x7 QFN package.
Features
* 3.3V Nominal Supply, Operates Down to 3.0V * DC-Coupled Outputs * Inputs can be AC- or DC-Coupled * Eliminates the Need for Large Output Coupling Capacitor * Integrated Sync Tip Clamp sets the Backporch to Ground at the Output for Channels 1 and 3 * Integrated Keyed Clamp puts Channel 2 and Channel 4 Outputs to Ground During Sync * Each Output Drives 2 Standard Video Loads * Response Flat to 5MHz with 40dB Attenuation at 27MHz * Pb-Free (RoHS compliant)
Applications
* Set-Top Box Receiver * Television * DVD Player * Digital Camera * Cell Phone
Ordering Information
PART NUMBER (NOTE) ISL59834IRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. # L44.7x7A
Block Diagram
ISL59834
CHANNEL 1
59 834IRZ -40 to +85 44 Ld QFN
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VIDEO IN (Y)
CLAMP + SYNC DETECTOR
LPF
x2
9MHz CHARGE PUMP CHANNEL 2
VIDEO OUT (Y)
VIDEO IN (C)
KEYED CLAMP
LPF
x2
9MHz CHARGE PUMP CHANNEL 3
VIDEO OUT (C)
VIDEO IN (Y)
CLAMP + SYNC DETECTOR
LPF
x2
9MHz CHARGE PUMP CHANNEL 4
VIDEO OUT (Y)
VIDEO IN (C)
KEYED CLAMP
LPF
x2
9MHz CHARGE PUMP
VIDEO OUT (C)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL59834 Pinout
ISL59834 (44 LD QFN) TOP VIEW
SYNC_OUTA SYNC_INA
ENABLEA
44 GND IN2 GND GNDCPA VCPA VS ENABLEB IN3 GND IN4 GND 1 2 3 4 5 6 7 8 9 10 11 12 NC
43
42
41
40
39
38
37
36
35
34 33 OUT2 32 VEEAIN 31 VEEAOUT 30 CAPA+ 29 CAPA28 CLKB 27 SYNC_OUTB 26 SYNC_INB 25 OUT3 24 OUT4 23 VEEBIN
13 NC
14 GNDCPB
15 VCPB
16 NC
17 NC
18 NC
19 CAPB-
20 CAPB+
21 NC
22 VEEBOUT
2
OUT1
CLKA
IN1
NC
NC
NC
NC
VS
FN6268.1 June 11, 2008
ISL59834
Absolute Maximum Ratings (TA = +25C)
VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VS + 0.3V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . 50mA Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .350V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 44 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150, Typical TA = +27C. CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
SYMBOL DC CHARACTERISTICS VS, VCP VEEOUT IS ICP IPD IIN IB AV VIN_MAX VCLAMPOUT1 VCLAMPOUT2 VCLAMPIN1 VCLAMPIN2 VOS
PARAMETER
Supply Range Charge Pump Output Supply Current Charge Pump Supply Current Power-down Current Input Pull-down Current Input Bias Current DC Gain Max DC Input Range Output Sync Tip Clamp Level (Channels 1 and 3) Keyed Clamp Level (Channels 2 and 4) Input Clamp Level (Channels 1 and 3) Input Keyed Clamp Level (Channels 2 and 4) Output Level Shift (Channels 1 and 3) Output Level Shift (Channels 2 and 4)
Guaranteed by PSRR Measured at VEEIN No load No load ENABLE = 0.4V Channels 1 and 3, VIN = 0.5V Channels 2 and 4, VIN = 0.5V, SYNC_IN = 0V
3.0 -1.75
3.3 -1.5 28 35 0.6
3.6 -1.25 32 40 5 10 10 2.05
V V mA mA A A A V/V V
0.4 -10 1.94
4 -3 2
DC-coupled input, guaranteed by DC gain test VIN 0, AC-coupled input Output level when SYNC_IN 2.0V Input floating Input floating, input level when SYNC_IN 2.0V VIN > 0, output shifted relative to input, DC-coupled input VIN > 0, output shifted relative to input, DC-coupled input Force VIN = -0.3V, Channels 1 and 3 Force VIN = 1V, Channel 2 and 4 Force VIN = -0.3V, Channels 2 and 4
1.4 -650 -60 0 275 -685 -380 -590 -25 30 300 -620 -330 -5 135 180 -200 100 50 77 -160 200 -525 0 70 375 -550 -280 -2.5
mV mV mV mV mV mV mA A A mV dB
ICLAMP
Clamp Restore Current
VSLICE PSRRDC
Sync Detect Threshold Power Supply Rejection
Channels 1 and 3 VS = +3.0 to +3.6
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FN6268.1 June 11, 2008
ISL59834
Electrical Specifications
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150, Typical TA = +27C. (Continued) CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT
SYMBOL AC CHARACTERISTICS APB ASB dG dP SNR GDMATCH GD PSRR XTALK VNOISE
PARAMETER
Passband Flatness Stopband Attenuation Differential Gain Differential Phase Signal-to-Noise Ratio DC Group Delay Match Group Delay Deviation Power Supply Rejection Channel-to-Channel Crosstalk Input Voltage Noise
f = 5MHz relative to 100kHz f 27MHz relative to 100kHz 11-step modulated staircase 11-step modulated staircase Peak signal (1.4VP-P) to RMS noise, f = 10kHz to 10MHz Channel-to-channel group delay matching at 100kHz Deviation from 100kHz to 3.58MHz VIN = 100mVP-P sine wave, f = 100kHz to 5MHz f = 100kHz to 5MHz, inter-channel
0
0.8 -50 0.45 -0.15 60 0.1 8 25 -55 1.44
1.25 -35
dB dB % dB ns ns dB dB mVRMS
LOGIC (ENABLEA, ENABLEB) VIL VIH II CHARGE PUMP fCP NOTE: 2. Parameters with MIN and/or MAX limits are 100% tested at +27C, unless otherwise specified. Temperature limits are established by characterization and are not production tested. Charge Pump Clock Frequency 9.5 MHz Logic Low Input Voltage Logic High Input Voltage Logic Input Current 2.0 -1 1 0.8 V V A
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FN6268.1 June 11, 2008
ISL59834 Pin Descriptions
NUMBER 1, 3, 9, 11 2 4 5 6, 41 7 8 10 12, 13, 16, 17, 18, 21, 35, 38, 40, 43 14 15 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 39 42 44 NAME GND IN2 GNDCPA VCPA VS ENABLEB IN3 IN4 NC GNDCPB VCPB CAPBCAPB+ VEEBOUT VEEBIN OUT4 OUT3 SYNC_INB SYNC_OUTB CLKB CAPACAPA+ VEEAOUT VEEAIN OUT2 OUT1 SYNC_INA SYNC_OUTA CLKA ENABLEA IN1 EP Ground Video Input 2. Chroma Channel. Charge Pump A Ground Charge Pump A Power Supply. Bypass with a 0.1F capacitor to GNDCPA. Positive Power Supply. Bypass to GND with a 0.1F capacitor. Channel 3 and Channel 4 Enable. Connect to VS to enable channels. ENABLEA must be tied to ENABLEB. Video Input 3. Luma Channel. Video Input 4. Chroma Channel. No Connect. Charge Pump B Ground. Charge Pump B Power Supply. Bypass with a 0.1F capacitor to GNDCPB. Charge-Pump B Flying Capacitor Negative Terminal. Connect a 0.1F capacitor from CAPB+ to CAPB-. Charge-Pump B Flying Capacitor Positive Terminal. Connect a 0.1F capacitor from CAPB+ to CAPB. Charge Pump Negative Output. Bypass with a 0.22F capacitor to GCP2. Negative Supply for Channels 3 and 4. Connect an RC filter between VEEBIN and VEEBOUT. See Typical Application Diagram. VEEAIN must be tied to VEEBIN. Video Output 4 Video Output 3 Sync Input. Sync logic input for Channel 4. Sync Output. Sync logic output from Channel 3. Channel 3 and Channel 4 Charge Pump Clock Output. Can also be driven by external clock. CLKA must be tied to CLKB. Charge-Pump A Flying Capacitor Negative Terminal. Connect a 0.1F capacitor from CAPA+ to CAPA-. Charge-Pump A Flying Capacitor Positive Terminal. Connect a 0.1F capacitor from CAPB+ to CAPB-. Charge Pump Negative Output. Bypass with a 0.22F capacitor to GNDCPA. Negative Supply for Channels 1 and 2. Connect an RC filter between VEEAIN and VEEAOUT. See Typical Application Diagram. VEEAIN must be tied to VEEBIN. Video Output 2 Video Output 1 Sync Input. Sync logic input for Channel 2. Sync Output. Sync logic output from Channel 1. Channel 1 and Channel 2 Charge Pump Clock Output. Can also be driven by external clock. CLKA must be tied to CLKB. Channel 1 and Channel 2 enable. Connect to VS to enable channels. ENABLEA must be tied to ENABLEB. Video Input 1. Luma Channel. Exposed Pad. Connect to VEEAIN or VEEBIN. FUNCTION
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FN6268.1 June 11, 2008
ISL59834 Functional Diagram
VS ENABLEA ENABLEB
SYNC_OUTA
SYNC DETECTOR
LPF IN1 9MHz
LEVEL SHIFT (-310mV)
X2
OUT1
VEEAIN + -593mV
LPF IN2 9MHz
LEVEL SHIFT (-165mV)
X2
OUT2
VEEAIN KEYED +
0V SYNC_INA
SYNC_OUTB
SYNC DETECTOR
LPF IN3 9MHz
LEVEL SHIFT (-310mV)
X2
OUT3
VEEBIN + -593mV
LPF IN4 9MHz
LEVEL SHIFT (-165mV)
X2
OUT4
VEEBIN KEYED +
VEEAIN VEEBIN
0V SYNC_INB
ISL59834
CHARGE PUMP A CHARGE PUMP B
GND
VEEAOUT
GNDCPA CAPA+ CAPA- CLKA
VCPA
VEEBOUT
GNDCPB CAPB+ CAPB- CLKB
VCPB
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FN6268.1 June 11, 2008
ISL59834 Component (YPbPr) Application Diagram
+3.3V
0.1F
4.7F
ENABLEA 0.1F IN1 150
ENABLEB
VS
SYNC_OUTA SYNC_INA SYNC_OUTB SYNC_INB 75 OUT1
CURRENT DAC
Y
CURRENT DAC
PB
0.1F IN2
75 75 OUT2 75
150
CURRENT DAC MPEG DECODER COMPOSITE SOURCE 75
PR
0.1F IN4 75 ISL59834 OUT3 75 75 IN3 OUT4 75 CLKA CLKB VEEAIN VEEBIN 10 VEEAOUT VEEBOUT 0.47F CS2 0.22F CFIL2 RFIL2
150
0.1F
RFIL1
10
0.22F CFIL1
CS1
0.47F
+3.3V VCPA 1.0F CCP1A 0.1F CCP1B GNDCPA GND CAPA+ CAPACF1 0.1F CAPB+ CAPBCF2 0.1F GNDCPB VCPB
+3.3V
0.1F CCP2A
1.0F CCP2B
s
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FN6268.1 June 11, 2008
ISL59834 S-Video Application Diagram
+3.3V
0.1F
4.7F
ENABLEA 0.1F Y1 75 IN1
ENABLEB
VS
SYNC_OUTA SYNC_INA SYNC_OUTB SYNC_INB 75
0.1F C1 75 IN2
OUT1 75 75 OUT2
0.1F Y2 75 IN3 75
75
ISL59834
0.1F IN4
OUT3 75 75 OUT4 75 CLKA CLKB
C2 75
VEEAIN RFIL1 10 VEEAOUT 0.22F CFIL1 CS1 0.47F
VEEBIN 10 VEEBOUT 0.47F CS2 0.22F CFIL2 RFIL2
+3.3V VCPA 1.0F CCP1A 0.1F CCP1B GNDCPA GND CAPA+ CF1 0.1F CAPACAPB+ CAPBCF2 0.1F GNDCPB VCPB
+3.3V
0.1F CCP2A
1.0F CCP2B
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FN6268.1 June 11, 2008
ISL59834 Typical Performance Curves
10 0
MAGNITUDE (dB) MAGNITUDE (dB)
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150.
2 1 CHANNEL 2, 4 RL = 75 CHANNEL 1, 3 RL = 75
-10 -20 -30 -40 -50 -60 -70 0.1 CHANNEL 1, 3 RL = 150 CHANNEL 1, 3 RL = 75 1M 10M FREQUENCY (Hz) 100M CHANNEL 2, 4 RL = 150 CHANNEL 2, 4 RL = 75
0 -1 -2 -3 -4 -5 0.1 1M FREQUENCY (Hz) 10M CHANNEL 1, 3 RL = 150 CHANNEL 2, 4 RL = 150
FIGURE 1. BANDWIDTH vs FREQUENCY
FIGURE 2. GAIN FLATNESS vs FREQUENCY
50
CHARGE PUMP VOLTAGE (V)
-1.40 CHANNEL 1, 3 LUMA -1.41 -1.42 -1.43 -1.44 -1.45 -1.46 -1.47 -1.48 2.7 VCP = 3.3V VS = 2.7V TO 3.6V 2.8 2.9 VS = 3.3V VCP = 2.7 TO 3.6V
40 30
DELAY (ns)
ALL MEASUREMENTS AT VEEIN
20 10 0 -10 -20 -30 -40 0.1 1M 10M FREQUENCY (Hz) 100M CHANNEL 2, 4 CHROMA
VCP = VS 2.7V TO 3.6V
3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V)
3.4
3.5
3.6
FIGURE 3. GROUP DELAY vs FREQUENCY
FIGURE 4. CHARGE PUMP VOLTAGE vs SUPPLY VOLTAGE
0 -10 -20
MAGNITUDE (dB)
0 ENABLE = LOW ANY INPUT TO ANY OUTPUT
MAGNITUDE (dB)
-10 -20 -30 -40 -50 -60 -70 -80
INPUT OF CHANNEL 1/2 TO OUTPUT OF CHANNEL 3/4
-30 -40 -50 -60 -70 -80 -90
-100 0.1
1M 10M FREQUENCY (Hz)
100M
-90 0.1
1M 10M FREQUENCY (Hz)
100M
FIGURE 5. INPUT-TO-OUTPUT ISOLATION vs FREQUENCY
FIGURE 6. INTER-CHANNEL CROSSTALK
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FN6268.1 June 11, 2008
ISL59834 Typical Performance Curves
0
SUPPLY CURRENT (mA)
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150. (Continued)
70 68 66 64 62 60 58 56 54 52 50 NO LOAD INPUT FLOATING
INPUT OF CHANNEL 1, 3 TO OUTPUT OF -10 CHANNEL 2, 4 AND VICE-VERSA
MAGNITUDE (dB)
-20 -30 -40 -50 -60 -70 0.1 1M 10M FREQUENCY (Hz) 100M
3.0
3.1
3.2 3.3 3.4 SUPPLY VOLTAGE (V)
3.5
3.6
FIGURE 7. LUMA-TO-CHROMA CROSSTALK
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
DISABLED SUPPLY CURRENT (nA)
1500 1400 1300 1200 1100 1000 900 800 700 600 500 3.0 3.1 3.2 3.3 3.4 SUPPLY VOTLAGE (V) 3.5 3.6 NO LOAD INPUT FLOATING
IMPEDANCE ()
30 25 20 15 10 5 0 0.1
1M
10M FREQUENCY (Hz)
100M
FIGURE 9. DISABLED SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY
0 -10
MAGNITUDE (dB)
0.05 0.03 0.01
DG (%)
VAC = 100mVP-P VS = +3.3V + VAC
WAVEFORM = MODULATED RAMP 0 IRE TO 100 IRE
-20 -30 -40 -50
-0.01 -0.03 -0.05 -0.07 -0.09 -0.11 -0.13 -0.15
-60 0.001
0.01
0.1 FREQUENCY (Hz)
1M
10M
0
1
2
3
4
5
6
7
8
9
10
11
STEP
FIGURE 11. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 12. DIFFERENTIAL GAIN
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FN6268.1 June 11, 2008
ISL59834 Typical Performance Curves
0.6 WAVEFORM = MODULATED RAMP 0.5 0 IRE to 100 IRE 0.4 0.3
DP ()
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150. (Continued)
TIME SCALE = 10ns/DIV DISABLE = 1V/DIV OUTPUT = 1V/DIV DISABLE SIGNAL
0.2 0.1 0 -0.1 -0.2 0 1 2 3 4 5 6 STEP 7 8 9 10 11 OUTPUT SIGNAL
FIGURE 13. DIFFERENTIAL PHASE
FIGURE 14. DISABLE TIME
TIME SCALE = 5s/DIV ENABLE = 1V/DIV OUTPUT = 1V/DIV
ENABLE SIGNAL
TIME SCALE = 500ns/DIV IN = 200mV/DIV OUT = 500mV/DIV INPUT
TIME = 35s
OUTPUT SIGNAL
OUTPUT
FIGURE 15. ENABLE TIME
FIGURE 16. 12.5T RESPONSE (CHANNELS 1 and 3)
TIMEBASE = 100ns/DIV IN = 200mV/DIV OUT = 500mV/DIV
TIME SCALE = 10s/DIV IN = 500mV/DIV OUT = 1V/DIV
INPUT INPUT
OUTPUT OUTPUT
FIGURE 17. 2T RESPONSE (CHANNELS 1 and 3)
FIGURE 18. NTSC COLORBAR (CHANNELS 1 and 3)
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FN6268.1 June 11, 2008
ISL59834 Typical Performance Curves
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150. (Continued)
LUMA OUTPUT CHANNELS 1, 3
TIME SCALE = 10s/DIV LUMA OUT = 500mV/DIV CHROMA OUT = 500mV/DIV
VIDEO SIGNAL (CHANNEL 1 or 3) TIME SCALE = 5s/DIV OUT = 500mV/DIV SYNC_OUT = 500mV/DIV
CHROMA OUTPUT CHANNELS 2, 4
SYNC_OUT
FIGURE 19. S-VIDEO SCOPE SHOT
FIGURE 20. SYNC_OUT SIGNAL
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)
INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)
CHANNEL 1 OR CHANNEL 3 OUTPUT
TIMEBASE = 1ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV
CHANNEL 1 OR CHANNEL 3 OUTPUT
TIMEBASE = 200s/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV
FIGURE 21. LUMA CLAMP RESPONSE TO POSITIVE TRANSIENT (CHANNEL 1 AND 3)
FIGURE 22. LUMA CLAMP RESPONSE TO NEGATIVE TRANSIENT (CHANNEL 1 AND 3)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)
INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR)
TIMEBASE = 2ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV CHANNEL 2 OR CHANNEL 4 OUTPUT
TIMEBASE = 2ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV
CHANNEL 2 OR CHANNEL 4 OUTPUT
FIGURE 23. CHROMA CLAMP RESPONSE TO POSITIVE TRANSIENT (CHANNEL 2 AND 4)
FIGURE 24. CHROMA CLAMP RESPONSE TO NEGATIVE TRANSIENT (CHANNEL 2 AND 4)
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FN6268.1 June 11, 2008
ISL59834 Typical Performance Curves
100 RMS NOISE = 2.87mV OUTPUT REFERRED 10 CHARGE PUMP NOISE, CONTRIBUTES ONLY A SMALL PERCENTAGE OF THE OVERALL NOISE
VCP = VS = 3.3V, CF1 = CF2 = 0.1F, CS1 = CS2 = 0.22F, CFIL1 = CFIL2 = 0.4F, CIN1 = CIN2 = CIN3 = CIN4 = 0.1F, RL1 = RL2 = 150. (Continued)
TIME SCALE = 50ns/DIV VERTICAL SCALE = 20mV/DIV
V/Hz
1 0.1
0M
1M
2M
3M
4M 5M 6M FREQUENCY (Hz)
7M
8M
9M
10M
FIGURE 25. NOISE SPECTRUM
FIGURE 26. CHARGE PUMP FEEDTHROUGH AT AMPLIFIER OUTPUT
4.5
POWER DISSIPATION (W)
0 VS = VCP = +3.3V -10 RL = 150 VOUT = 0 TO 2VP, SINE WAVE -20
THD (dBc)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 AMBIENT TEMPERATURE (C) 44 LD QFN PACKAGE 7mmx7mm JA = +32C/W
-30 -40 -50 -60 -70 0.5 0.8 1.1 1.4 1.7 2.0 fIN = 500kHz fIN = 5MHz
OUTPUT VOLTAGE (V)
FIGURE 27. THD (dBc) vs OUTPUT VOLTAGE (VP-P)
FIGURE 28. PACKAGE POWER DISSIPATION
Description of Operation and Application Information Theory of Operation
The ISL59834 is a single supply video driver with a reconstruction filter and an on-board charge pump. It is designed to drive SDTV displays with component (YPbPr), S-video (Y-C), or composite video (CV) signals. The input signals can be AC or DC-coupled. When AC-coupled, a sync tip clamp sets the blank level to ground at the output of Channel 1 and Channel 3. Keyed clamps force the average levels of Channel 2 and Channel 4 to ground. The keyed clamps force the outputs to ground when SYNC_INA or SYNC_INB are driven to the logic high state. The ISL59834 outputs are capable of driving two AC or DC-coupled standard video loads and have a 4th order Butterworth reconstruction filter with nominal -3dB frequency set to 9MHz, providing 40dB of attenuation at 27MHz. The ISL59834 is designed to operate with a single supply voltage range ranging from 3.0V to 3.6V. This eliminates the need for a split supply with the incorporation of two charge pumps capable of generating a bottom rail as much as 1.5V below ground; providing a 4.8V range on a single 3.3V supply. This performance is ideal for NTSC video with negative-going sync pulses.
Output Amplifier
The ISL59834 output amplifiers provide a gain of +6dB. The output amplifiers are able to drive a 2.8VP-P video signal into a 150 or 75 load to ground. The outputs are highly-stable, low distortion, low power, high frequency amplifiers capable of driving moderate (~10pF) capacitive loads.
Input/Output Range
The ISL59834 has a dynamic input range of 0 to 1.4VP-P This allows the device to handle high amplitude video signal inputs. As the input signal moves outside the specified range, the output signal will exhibit increasingly higher levels of harmonic distortion.
Charge Pump
The ISL59834 contains two charge pumps; charge pump A supplies Channel 1 and 2, while charge pump B supplies Channel 3 and 4. The ISL59834 charge pumps provide a bottom rail up to 1.5V below ground while operating on a 3.0V to 3.6V power supply. The charge pumps are internally regulated and are driven by internal 9.5MHz clocks. The
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FN6268.1 June 11, 2008
ISL59834
clock pins for both charge pumps (CLKA and CLKB) must be shorted together. To reduce the noise on the power supply generated by the charge pump, connect a lowpass RC-network between VEEOUT and VEEIN. See the "Typical Application Circuits" for further information.
AC-Coupled Inputs
SYNC TIP CLAMP (CHANNEL 1 AND 3) The ISL59834 features a sync tip clamp that forces the black level of the output video signal to ground. This ensures that the sync-tip voltage level will be approximately -300mV at the back-termination resistor of a standard video load. The clamp is activated whenever the input voltage falls below 0V. The correction voltage required to do this is stored across the input AC-coupling capacitor. Refer to Typical Application Circuit for a detailed diagram. KEYED CLAMP (CHANNEL 2 AND 4) Channel 2 and Channel 4 have a keyed clamp, which forces the output to ground when SYNC_INA (Channel 2) or SYNC_INB (Channel 4) are driven to the logic high state. The SYNC_IN pins may be connected to either SYNC_OUT pins or they may be driven by external sources. SYNC DETECTOR AND CLAMP TIMING Channel 1 and Channel 3 also have sync detectors whose outputs are available at SYNC_OUTA and SYNC_OUTB pins respectively. The slice level for the sync detectors is between 100mV to 200mV. This means that if the signal level is below 100mV at Channel 1 or 3, then SYNC_OUTA or SYNC_OUTB are high. If the signal level is above 200mV, then SYNC_OUTA or SYNC_OUTB are low. Figure 29 shows the operation of the sync detector.
NTSC LUMINANCE CHANNEL 1 OR 3 INPUT +1.00V
VEEOUT Pins
VEEAOUT and VEEBOUT are the output pins for the charge pumps. Keep in mind that these outputs are fully regulated supplies that must be properly bypassed. Bypass these pins with a 0.47F ceramic capacitor placed as close to the pin and connected to the ground plane of the board.
VEEIN Pins
VEEAIN and VEEBIN are the subtrate connections for the ISL59834, these two pins must be shorted together. To reduce the noise on the power supply generated by the charge pump, connect a lowpass RC-network between VEEOUT and VEEIN. See the "Typical Application Circuits" for further information.
Video Performance
DIFFERENTIAL GAIN/PHASE For good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as DC levels are changed at the output. Special circuitry has been incorporated into the ISL59834 to reduce the output impedance variation with the current output. This results in outstanding differential gain and differential phase specifications of 0.45% and 0.15, while driving 150 at a gain of +2V/V. NTSC The ISL59834, generating a negative rail internally, is ideally suited for NTSC video with its accompanying negative-going sync signals. S-VIDEO For a typical S-video application with two S-video signals, connect the luma signals to Channel 1 and 3, and connect the chrominance signals to Channel 2 and 4. For clamp timing, connect SYNC_OUTA to SYNC_INA and SYNC_OUTB to SYNC_INB. See the "S-Video Typical Application Circuit" on page 8. YPbPr For a typical component video application, connect Y to Channel 1, Pb to Channel 2 and Pr to Channel 4. Channel 3 can be optionally used a composite signal. For the clamp timing, connect SYNC_OUTA to both SYNC_INA and SYNC_INB and leave SYNC_OUTB floating. See the "YPbPr Typical Application Circuit" on page 7.
+300mV 100mV < VSLICE < 200mV +0mV SYNC_OUTA OR SYNC_OUTB +3.3V +0mV
FIGURE 29. SYNC DETECTOR SLICE LEVEL
DC-Coupled Inputs (Channel 1 and 3)
When DC-coupling the inputs, ensure that the lowest signal level is greater than +50mV to prevent the clamp from turning on and distorting the output. When DC-coupled, the ISL59834 shifts the signal by -620mV.
Amplifier Disable
The ISL59834 can be disabled and its output placed in a high impedance state. ENABLEA shuts off Channel 1 and 2 while ENABLEB shuts off Channel 3 and 4. Both ENABLE pins must be shorted together. The turn-off time is around 10ns and the turn-on time is around 35s. The turn-on time
FN6268.1 June 11, 2008
14
ISL59834
is longer because extra time is needed for the charge pump to settle before the amplifiers are enabled. When disabled, the device supply current is reduced to 5A. Power-down is controlled by standard TTL or CMOS signal levels at the ENABLE pins. The applied logic signal is relative to the GND pin. Applying a signal that is less than 0.8V above GND will disable the device. The device will be enabled when the ENABLE signals are 2V above GND. Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current i = Number of output channels By setting Equation 1 equal to Equation 2 and 3, we can solve for the output current and RLOAD values needed to avoid exceeding the maximum junction temperature.
Output Drive Capability
The maximum output current for the ISL59834 is 50mA. Maximum reliability is maintained if the output current never exceeds 50mA, after which the electro-migration limit of the process will be exceeded and the part will be damaged. This limit is set by the design of the internal metal interconnections.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Strip line design techniques are recommended for the input and output signal traces to help control the characteristic impedance. Furthermore, the characteristic impedance of the traces should be 75. Trace lengths should be as short as possible between the output pin and the series 75 resistor. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS and VCP to GND will suffice. The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * Use low inductance components, such as chip resistors and chip capacitors whenever possible. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners; use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces longer than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. To maintain frequency performance with longer traces, use striplines. * Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Route all signal I/O lines over continuous ground planes (i.e. no split planes or PCB gaps under these lines). * Place termination resistors in their optimum location as close to the device as possible.
Driving Capacitive Loads and Cables
The ISL59834 (internally-compensated to drive 75 cables) will drive 10pF loads in parallel with 150 or 75 with less than 1.3dB of peaking.
Power Dissipation
With the high output drive capability of the ISL59834, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 1)
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing:
V OUT i PDMAX = V S x I SMAX + ( V S - V OUT i ) x --------------------R i
LOAD
(EQ. 2)
for sinking:
PD MAX = V S x I SMAX + ( V OUT i - V S ) x I LOAD i (EQ. 3)
15
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ISL59834
* Use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum when testing. * Place flying and output capacitors as close to the device as possible for the charge pump. Decouple well, using a minimum of 2 power supply decoupling capacitors, placed as close to the device as possible. Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger capacitors may be farther away. When vias are required in a layout, they should be routed as far away from the device as possible.
16
FN6268.1 June 11, 2008
ISL59834 Quad Flat No-Lead Plastic Package (QFN)
L44.7x7A
A N (N-1) (N-2) D B
44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL MIN 0.80 0.00 0.20 NOMINAL 0.85 0.02 0.25 0.203 REF 7.00 BASIC 5.10 REF 7.00 BASIC 5.10 REF 0.50 BASIC 0.50 0.55 44 REF 11 REF 11 REF 0.60 MAX 0.90 0.05 0.30 NOTES 8 8 4 6 5 Rev. 1 1/07 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. A
1 2 3
PIN #1 I.D. MARK
E
A1 b c D D2 E E2 e L N ND NE
(2X) 0.075 C (N/2) 0.075 C TOP VIEW
C SEATING PLANE
e
0.10 C
(2X)
0.08 C N LEADS AND EXPOSED PAD
SEE DETAIL "X" SIDE VIEW
0.01 M C A B
L N LEADS b (N-2) (N-1) N PIN #1 I.D.
3
1 2 3
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown.
(E2)
NE 5 (N/2)
8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 9. One of 10 packages in MDP0046
(D2) BOTTOM VIEW
7
C
A
(c)
2
A1 DETAIL "X"
(L) N LEADS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN6268.1 June 11, 2008

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